PCIe Physical Layer Interview Questions on Gen 2 or Gen 3 or Gen 4
1. Why PCIe is a serial protocol? 2. Why do we use scrambling in PCIe? 3. Why do we use 8b/10b or 128b/130b encoding in PCIe Gen 3 or Gen 4? 4. Is scrambling not enough? Why do we still go for 8b/10b or 128b/130b encoding in PCIe? 5. What is DC balance? 6. Which symbols are not scrambled in PCIe? 7. When is scrambling re-started? 8. What is difference between pre-emphasis and de-emphasis? 9. Why do we use pre-emphasis in PCIe? 10. Any connection between equalization and pre-emphasis? 11. Why do we need to replicate Ordered Sets on all lanes? 12. Difference between logical idle and electrical idle? 13. Difference between PAD and IDL? 14. Why SKP is ignored by scrambler? 15. Why do we need Tx or Rx buffers in Physical Layer of PCIe? 16. What is significance of elastic buffer in PCIe physical layer?