ASIC Design Verification Interview Questions

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Why assertions? Where do we write them? What is bind? What is assume? Difference between assert and assume? What is expect? Difference between sequence and property? Practical difference between immediate and concurrent assertions? Can we write assertions in interface and class? Difference between overlapping and non-overlapping assertions? How to assert only once? Special use of assertion coverage? Write an assertion: A high for 5 cycles and B high after 4 non-continuous highs of A and finally both A and B are high? ____|====|_____|======================|______   A ________________________________|=====|______   B

Difference between AHB and AXI? Difference between AXI3 and AXI4? What is AXI Lite? Name five special features of AXI? Why streaming support,it's advantages? Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction  What is the AXI capability of data interleaving? Explain out-of-order transaction support on AXI? Explain multiple outstanding address pending? Any flow control mechanism in AXI? How to ensure data integrity on AXI? What is 'last' signal? What are bursts and transfers? Maximum size of a transfer? Write response codes? What is strobing in AXI?

1. What are the functions performed by software layer in PCIe? 2. Difference between gen 2 and gen 3 PCIe protocols? 3. Functions of transaction and data link layers? 4. How FC credits mechanism works? 5. Difference between posted and non-posted transactions? 6. What is split transaction mechanism in PCIe? 7. Why do we need DLLPs? 8. How to corrupt PCIe packets? 9. Different types of routing mechanisms in PCIe? 10. How message packets are routed? 11. What is implicit routing? 12. Which types of packets are routed by ID?

1. Significance of TD bit in packet header? 2. Why only Memory Write transactions are posted and why not IO Write transactions? 3. Difference between PCI and PCIe [PCI express]? 4. In which state of LTSSM, Gen 2 and Gen 1 speeds of different PCIe links handled? 5. Why 8b/10b encoding in PHY? 6. WhyPCIe is a serial protocol,why not parallel? 7. What is the size of IO read packet's requested data? 8. Which layer of PCIe has flow control mechanism? 9. Explain flow control mechanism 10. Difference between InitFC and UpdateFC DLLPs? 11. Difference between Cfg0 and Cfg1 packets,read or write ? 12. Difference between PCIe and RapidIO [SRIO] ? 13. What is enumeration in PCIe?