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Showing posts with the label mobiveil

System Verilog Assertions(SVA) Interview Questions - smartplay and mobiveil

Why assertions? Where do we write them? What is bind? What is assume? Difference between assert and assume? What is expect? Difference between sequence and property? Practical difference between immediate and concurrent assertions? Can we write assertions in interface and class? Difference between overlapping and non-overlapping assertions? How to assert only once? Special use of assertion coverage? Write an assertion: A high for 5 cycles and B high after 4 non-continuous highs of A and finally both A and B are high? ____|====|_____|======================|______   A ________________________________|=====|______   B

AMBA AXI Protocol Interview Questions - Xilinx, Sicon, Ensilica and Mobiveil

Difference between AHB and AXI? Difference between AXI3 and AXI4? What is AXI Lite? Name five special features of AXI? Why streaming support,it's advantages? Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction  What is the AXI capability of data interleaving? Explain out-of-order transaction support on AXI? Explain multiple outstanding address pending? Any flow control mechanism in AXI? How to ensure data integrity on AXI? What is 'last' signal? What are bursts and transfers? Maximum size of a transfer? Write response codes? What is strobing in AXI?