System Verilog Assertions(SVA) Interview Questions - smartplay and mobiveil

Why assertions?

 Where do we write them?

 What is bind?

 What is assume?

 Difference between assert and assume?

 What is expect?

 Difference between sequence and property?

 Practical difference between immediate and concurrent assertions?

 Can we write assertions in interface and class?

 Difference between overlapping and non-overlapping assertions?

 How to assert only once?

 Special use of assertion coverage?

 Write an assertion: A high for 5 cycles and B high after 4 non-continuous highs of A and finally both A and B are high?

 ____|====|_____|======================|______   A

 ________________________________|=====|______   B



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