PCIe Interview Questions - SmartPlay and Xilinx


1. Significance of TD bit in packet header?

2. Why only Memory Write transactions are posted and why not IO Write transactions?

3. Difference between PCI and PCIe [PCI express]?

4. In which state of LTSSM, Gen 2 and Gen 1 speeds of different PCIe links handled?

5. Why 8b/10b encoding in PHY?

6. WhyPCIe is a serial protocol,why not parallel?

7. What is the size of IO read packet's requested data?

8. Which layer of PCIe has flow control mechanism?

9. Explain flow control mechanism

10. Difference between InitFC and UpdateFC DLLPs?

11. Difference between Cfg0 and Cfg1 packets,read or write ?

12. Difference between PCIe and RapidIO [SRIO] ?

13. What is enumeration in PCIe?






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